1. Field of the Invention
The present invention relates to the field of synchronization mechanisms within a clock network, and in particular to clock synchronization mechanisms for integrated circuit designs.
2. Description of the Related Art
FIG. 1 illustrates a clock distribution network 50 within an integrated circuit (IC) 20. A clock signal is supplied to network 50 via an external pad 10. Data is supplied via other external pads (not shown). In this case, network 50 branches out throughout IC 20 from a center point 55. Network 50, as is known in the art, functions to evenly supply the clock signal throughout IC 20 so that at supply points within network 50 the clock signals are supplied without skew. Skew is defined as the difference in delays between clock signals which results in a difference in arrival times. Network 50 and specifically the supply points within network 50 are determined so that the clock signal from pad 10 propagates along a relatively common distance from pad 10 to any supply point.
In this manner, the signal delay is roughly the same between the reference clock signal at pad 10 and any supply point in network 50. Network 50 is said to "deskew" the clock, and the clock signal obtained at any point along network 50 is said to be "deskewed." In accordance with the above, clock signals obtained from any two supply points along network 50 should have marginal or negligible skew between them.
Although the clock signal from network 50 is "deskewed" relative to any two supply points, the deskewed signal is nevertheless delayed relative to the input clock signal seen at pad 10. For instance, although an input/output block (IOB) 15 is placed relatively close to pad 10, IOB 15 nevertheless does not receive the clock signal over network 50 until the signal propagates through length 50a (half of the chip length), through length 50b (roughly half of the chip length), through length 50c (roughly half of the chip length) and through length 50d. Each length introduces signal delay relative to the clock signal seen at pad 10.
This clock delay can be problematic for circuits such as IOB 15. As is known in the art, IOBs interface with input and output pads of IC 20 and route signals to or from other internal circuitry of the chip. In some cases, it is desirable for IOB 15 to receive the input clock signal without delay relative to pad 10. For instance, in some cases it is desired to reduce the chip hold time on input data so as to efficiently interface with external systems that supply data. Data delay is typically used to eliminate such hold times. However, manufacturing uncertainties require excessive delay to compensate for worst case delays and increases set-up times unnecessarily. Minimizing clock distribution delay minimizes this compensating delay, thereby reducing the uncertainty and the ill-effects of worst case delays.
Therefore, a need arises for a mechanism allowing certain circuitry within an IC to receive a clock signal with negligible delay relative to the input signal at the clock pad. Moreover, a need arises for a mechanism allowing the certain circuitry to interface with other IC elements that use a standard delayed clock. The present invention provides the above advantageous functionalities.